1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof.
2. Description of the Related Art
A constitution of a DRAM memory cell to be used in a semiconductor device, particularly a DRAM (Dynamic Random Access Memory) or a logic-embedded DRAM etc., as well as a method of manufacturing such memory cell have been disclosed in Japanese Patent laid open No.2003-007854.
FIG. 8 is a schematic cross-sectional view showing a memory cell region formed in a conventional DRAM. Here, since transistors are similar to those disclosed in the cited document, detailed description thereof will be omitted.
A DRAM memory cell is provided with a transistor formed on a semiconductor substrate 100 and a capacitance formed on the transistor via an interlayer dielectric film. As shown in FIG. 8, contact plugs are employed to electrically connect a source electrode 112 of the transistor and the capacitance. The contact plugs include a cell contact plug formed between the transistor and a bit line, which is an interconnect for applying a voltage to a drain electrode 114 of the transistor, and a capacitance contact plug 270 for connecting the cell contact plug and the capacitance.
The cell contact plug is classified into a first cell contact plug 250 for connecting the drain electrode 114 of the transistor and the bit line, and a second cell contact plug 252 connected to the capacitance contact plug 270.
The source electrode 112 and the drain electrode 114 of the transistor are constituted of an impurity diffusion layer formed by diffusing an impurity on a surface of the semiconductor substrate, and a lateral face of the source electrode 112 and the drain electrode 114 in the semiconductor substrate is covered with an isolation dielectric layer 116 except in an active region, which is not shown.
The capacitance is provided with a lower electrode 180 for accumulating charge therein, an upper electrode 184 to serve as a plate electrode, and a dielectric 182 disposed between the lower electrode 180 and the upper electrode 184. The lower electrode 180 is connected to the capacitance contact plug 270.
Also, the first cell contact plug 250 and the second cell contact plug 252 are electrically insulated by a silicon oxide layer 104. Likewise, a first bit line 260, a second bit line 262, a third bit line 264 and the capacitance contact plug 270 are electrically insulated from one another, by a silicon oxide layer 105 and a silicon oxide layer 106.
A method of manufacturing such a semiconductor device will be described below.
As shown in FIG. 9A, the isolation dielectric layer 116 is first formed on the semiconductor substrate 100, and the transistor provided with the source electrode 112 and the drain electrode 114 etc. is formed, after which a silicon nitride layer 102 and a silicon oxide layer 104 are formed. Then a cell contact hole 230 for later forming a cell contact plug therein is formed in the silicon nitride layer 102 and the silicon oxide layer 104, by a known lithography and etching process, and a titanium nitride (TiN) layer 254 and a tungsten (W) layer 256, are filled in the cell contact hole 230 to act as conductive layers, and also formed on the silicon oxide layer 104. Thereafter CMP (Chemical Mechanical Polishing) is performed to remove the conductive layers on the silicon oxide layer 104, so that the first cell contact plug 250 and the second cell contact plug 252 are formed.
Then, plasma CVD (Chemical Vapor Deposition) is carried out to form the silicon oxide layer 105, to ensure insulation between the second cell contact plug 252 and the bit line, and a bit contact hole 232 is formed in the silicon oxide layer 105 at a position corresponding to the first cell contact plug 250, by a known lithography and etching process. And a TiN layer 266 and a W layer 268 are successively formed to constitute conductive layers (FIG. 9B).
Thereafter, in order to form the bit line from the conductive layers, a resist 290 is formed by a known lithography process, and anisotropic etching is performed on the TiN layer 266 and the W layer 268 to form the first bit line 260, the second bit line 262 and the third bit line 264 (FIG. 9C).
After removing the resist 290, the silicon oxide layer 106 shown in FIG. 8 is formed. Then the capacitance contact plug 270 shown in FIG. 8 is formed in the silicon oxide layer 106 by a method similar to forming the cell contact plug. Then, an SiON layer 108 and a silicon oxide layer 110 are formed, and a capacitance opening is formed in the SiON layer 108 and the silicon oxide layer 110 at a position corresponding to the capacitance contact plug 270, by a known lithography and etching process. Now after forming a TiN layer that serves as the lower electrode 180 on a bottom portion and a side wall of the capacitance opening, an insulation layer to serve as a dielectric is formed and further an impurity-diffused polysilicon layer is buried in the capacitance opening. Then, the dielectric 182 and the upper electrode 184 are formed by a known lithography and etching process. Finally the semiconductor device is completed upon forming an interlayer dielectric film and providing an interconnect among the elements and a protection layer, which are not shown.
According to the foregoing method of manufacturing, the silicon oxide layer 105 is provided as the interlayer dielectric film, to better ensure insulation between the bit line and the second cell contact plug, and the bit contact hole is formed to connect the first cell contact plug and the first bit line. This requires a lithography process and an etching process to form the bit contact hole in the silicon oxide layer 105, which results in a drawback that a manufacturing period of the semiconductor device is prolonged because of an increase in the number of process.
Besides, in case where the capacitance contact plug is formed in a downwardly tapered shape as shown in FIG. 8, an area of a cross-section orthogonal to a direction toward the second cell contact plug from inside the capacitance contact plug, becomes smaller at a position closer to the second cell contact plug. Accordingly, the greater a distance between the second cell contact plug and the lower electrode of the capacitance is, the smaller a contact area of the second cell contact plug and the capacitance contact plug becomes. Consequently, in case where the silicon oxide layer 105 is provided as the interlayer dielectric film as described above, since a distance between the second cell contact plug and the lower electrode inevitably becomes as much greater, a contact area between the plugs becomes smaller, resulting in an increase of resistance.